os/arch/riscv/trap/
mod.rs1mod sum_guard;
5mod trap_frame;
6mod trap_handler;
7
8use core::arch::global_asm;
9use riscv::register::{
10 mtvec::TrapMode,
11 stvec::{self, Stvec},
12};
13
14pub use sum_guard::SumGuard;
15pub use trap_frame::TrapFrame;
16
17global_asm!(include_str!("trap_entry.S"));
18global_asm!(include_str!("boot_trap_entry.S"));
19global_asm!(include_str!("sigreturn.S"));
20
21pub fn init_boot_trap() {
23 set_boot_trap_entry();
24}
25
26pub fn init() {
28 set_trap_entry();
29}
30
31pub unsafe fn restore(trap_frame: &TrapFrame) {
35 unsafe { __restore(trap_frame) };
36}
37
38pub fn sigreturn_trampoline_address() -> usize {
40 __sigreturn_trampoline as usize
41}
42
43fn set_trap_entry() {
44 unsafe {
46 stvec::write(Stvec::new(trap_entry as usize, TrapMode::Direct));
47 }
48}
49
50fn set_boot_trap_entry() {
51 unsafe {
53 stvec::write(Stvec::new(boot_trap_entry as usize, TrapMode::Direct));
54 }
55}
56
57unsafe extern "C" {
58 unsafe fn boot_trap_entry();
59 unsafe fn trap_entry();
60 unsafe fn __restore(trap_frame: &TrapFrame);
61 unsafe fn __sigreturn_trampoline();
62}